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Overview

Temporal Address Mapping Specification

Status: STUB Priority: P3 Document ID: design-001 Canonical Path: docs/design/Temporal_Address_Mapping_Spec.md Related Module: docs/post-ASML_era/module.json

About This Document#

This document is a planned stub. It has been registered in the TriadicFrameworks documentation graph and is referenced by one canonical post-ASML era document. It is a P3 priority deliverable — important for completeness but not a prerequisite for any other P1 or P2 documents.

Purpose#

The Temporal Address Mapping Specification defines how logical temporal addresses — abstract identifiers for temporal commit positions within a TRS-aware design — are mapped to physical zone-relative commit positions within an SCR topology. This mapping is a prerequisite for multi-zone logic folding, inter-zone arc routing, and any design that spans more than one SCR zone. It bridges the architectural abstraction layer (Logic Folding Architecture Guide) and the physical SCR topology (SCR Zone Configuration Guide).

Citing Documents#

Document Context of Citation
docs/post-ASML_era/The_Multi-Regime_Semiconductor_Model.md Referenced in the context of observable parameter derivations: temporal address resolution is required to assign modeled ψ(r,t) values to physical commit points for model validation; regime boundary positions in physical coordinates are consumed by the address mapping layer

Expected Content#

When authored, this document is expected to cover:

  1. Addressing Model Overview — Motivation for a two-level (logical/physical) temporal address space; analogy to virtual memory address translation; scope of this specification.
  2. Logical Temporal Address Space
    • Address structure: zone ID field, fold depth field, commit slot field, phase offset field
    • Address width constraints; maximum zone count and commit slot count
    • Null address and broadcast address conventions
  3. Physical SCR Commit Position
    • Physical coordinate representation: zone ID, CDN segment, CCG phase window, SLF frame offset
    • Physical address resolution to hardware commit arbiter (CA) queue slot
  4. Address Translation Table (ATT)
    • ATT structure and population procedure
    • Static vs. dynamic ATT entries
    • ATT consistency requirements across zones (inter-zone coherence of address mappings)
    • ATT storage format; relationship to TLMF zone boundaries
  5. Translation Procedure
    • Lookup algorithm: logical → physical in O(1) for static mappings
    • Collision handling: two logical addresses mapping to the same physical slot
    • Phase offset resolution and rounding rules
  6. Zone Boundary Crossing
    • Address translation for ZBA arcs that cross zone boundaries
    • SLF re-synchronization at zone crossing; latency budget accounting
    • Forbidden address ranges at zone boundaries (exclusion zones)
  7. Multi-Zone Address Coherence
    • Requirements for globally consistent logical address assignment across a multi-zone fabric
    • Address space partitioning by zone: non-overlapping partition requirement
    • Cross-zone address validation procedure
  8. Integration with Logic Folding
    • How fold depth field in logical address maps to physical fold stage in Logic Folding Architecture
    • Temporal Register (TR) address encoding conventions
    • Inter-fold ZBA arc source/destination address encoding
  9. Integration with SCR Zone Configuration
    • ATT initialization from SCR zone topology (from docs/fab/SCR_Zone_Config.md)
    • Reconfiguration impact on ATT entries; ATT invalidation and re-population procedure
  10. Normative Requirements Summary — Consolidated table of all MUST/SHOULD/MAY requirements with R-TAMS-NN identifiers.

Dependencies#

When authored, this document is expected to reference:

  • docs/post-ASML_era/The_Logic_Folding_Architecture_Guide.md — Logical address field definitions come from fold architecture definitions
  • docs/fab/SCR_Zone_Config.md — Physical zone topology that ATT entries map into
  • docs/post-ASML_era/The_SCR_Specification.md — Commit Arbiter (CA) queue structure that physical addresses resolve to
  • docs/eda/TTF_Reference.md — ZBA arc encoding that carries temporal addresses in TTF format
  • docs/data-formats/TLMF_Schema.md — TLMF zone boundaries used in ATT initialization

Authoring Notes#

  • This document MUST use normative language with R-prefix identifiers (R-TAMS-NN format recommended).
  • The two-level addressing model (logical/physical) MUST be precisely defined before any translation procedure is described.
  • Address field widths MUST be stated as normative constraints with explicit maximums; unspecified widths create interoperability failures.
  • The relationship to TLMF zone IDs and to TTF ZBA arc source/destination fields MUST be made explicit with cross-document field-name mappings.
  • This document is P3 priority — it may be deferred until P1 and P2 documents are complete, but it should be authored before any multi-zone design validation work begins.
Document Relationship
docs/post-ASML_era/The_Logic_Folding_Architecture_Guide.md Primary architectural consumer — fold stages use temporal addresses
docs/post-ASML_era/The_SCR_Specification.md Physical target — CA queue slots are the physical commit positions
docs/fab/SCR_Zone_Config.md Zone topology source for ATT initialization
docs/eda/TTF_Reference.md TTF ZBA arc carries temporal address fields defined here
docs/data-formats/TLMF_Schema.md TLMF zone IDs align with logical address zone ID field
docs/post-ASML_era/The_Multi-Regime_Semiconductor_Model.md Regime map consumer — physical addresses anchor ψ(r,t) validation points
docs/post-ASML_era/README.md Module index

This stub was scaffolded from the TriadicFrameworks post-ASML era documentation suite. See docs/post-ASML_era/README.md for the full document graph.

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