TRS Stack Qualification Procedure

Document ID: fab-001 Canonical Path: docs/fab/TRS_Qualification.md Revision: 1.0.0 Status: CANONICAL Type: Procedure Normative: Yes Updated: 2026-08-08 Maintainer: TriadicFrameworks

Table of Contents#

1. Purpose and Scope
2. Normative Language
3. Qualification Overview and Gate Structure
4. Prerequisites and Entry Conditions
5. Instrument Requirements
6. Test Coupon Requirements
7. L1 Intent Layer Qualification
8. L2 Sequencing Layer Qualification
9. L3 Resolution Layer Qualification
10. L4 Commit Layer Qualification
11. Full-Stack Integration Test
12. Acceptance Criteria by SC Class
13. Disqualification, Remediation, and Re-Qualification
14. Documentation and Sign-Off
15. Integration with SCR Commissioning
16. Glossary
17. Related Documents

1. Purpose and Scope#

1.1 Purpose#

This document is the normative procedure for qualifying a Temporal Resolution Stack (TRS) installation across all four operator layers — L1 Intent, L2 Sequencing, L3 Resolution, and L4 Commit — in a production post-ASML fab environment. Successful completion of this procedure is the mandatory prerequisite for SCR zone commissioning, for any silicon lot entering temporal manufacturing operations, and for tapeout sign-off eligibility under the TRS-Aware PDK.

The TRS qualification procedure establishes that:

• Each individual TRS operator layer functions within its specified fidelity limits.
• The four layers function correctly as a composed stack.
• The stack's performance is consistent with the SC class of the substrate lot on which qualification is being performed.
• The qualification evidence is traceable, reproducible, and sufficient to support the downstream claims made by the SCR Specification and the TRS-Aware PDK Specification.

1.2 Scope#

This procedure applies to:

• New TRS installations at any TriadicFrameworks-aligned fab.
• TRS installations following equipment replacement at one or more layers.
• TRS installations following a major firmware update at L1, L2, L3, or L4.
• TRS installations following any Coherence-Loss Event (CMA Level 3 alert) as defined in docs/post-ASML_era/The_SCR_Specification.md, §9.2.5.
• Periodic re-qualification as specified in §13.3.

This procedure does not govern:

• Individual instrument calibration, which is governed by docs/post-ASML_era/TCT_Protocol.md and docs/post-ASML_era/The_TGI_Metrology_Standard.md.
• SCR zone commissioning, which follows this procedure and is governed by docs/fab/SCR_Zone_Config.md.
• SC class assignment, which is governed by docs/materials/SC_Classification.md.

1.3 Position in the Commissioning Sequence#

SC_Classification.md          TCT_Protocol.md
  (lot SC class assignment)   (measurement traceability)
          │                            │
          └──────────────┬─────────────┘
                         │
                         ▼
               TRS_Qualification.md   ← THIS DOCUMENT
               (L1 → L2 → L3 → L4 sequential gate)
                         │
                         ▼
               SCR_Zone_Config.md
               (zone commissioning)
                         │
                         ▼
               The_TRS-Aware_PDK_Specification.md
               (PDK certification)

No SCR zone may be commissioned for production until the TRS qualification for that zone's substrate lot is signed off under this procedure.

2. Normative Language#

Requirement identifiers use the format R-TRSQ-NN, where TRSQ denotes the TRS Qualification procedure and NN is a two-digit sequential number. Requirements are normative obligations on any entity executing or reviewing this qualification procedure.

3. Qualification Overview and Gate Structure#

3.1 The Sequential Gate Model#

TRS qualification proceeds as a strictly sequential set of four layer-level gates, followed by a full-stack integration test. Each gate must be passed before the next gate is opened.

  ┌──────────────────────────────────────────────────────────────────┐
  │                  TRS QUALIFICATION GATE SEQUENCE                 │
  │                                                                  │
  │  [Prerequisites] → [L1 Gate] → [L2 Gate] → [L3 Gate]           │
  │                                                → [L4 Gate]       │
  │                                                → [Full-Stack]    │
  │                                                → [Sign-Off]      │
  └──────────────────────────────────────────────────────────────────┘

R-TRSQ-01 The four layer qualification gates MUST be executed in the order L1 → L2 → L3 → L4. Execution of a gate for layer L(n+1) before L(n) has passed is non-conformant regardless of the apparent readiness of L(n+1).

R-TRSQ-02 A gate failure at any layer MUST halt the qualification sequence. The qualification procedure cannot continue to later layers while a gate failure is unresolved. The failure disposition procedure of §13 applies.

3.2 What Each Gate Verifies#

3.3 Qualification Substrate Requirement#

R-TRSQ-03 TRS qualification MUST be performed on a substrate lot with a valid SC class assignment issued under docs/materials/SC_Classification.md before qualification begins. The SC class of the qualification lot determines which acceptance criteria table applies (§12).

R-TRSQ-04 Qualification performed on a substrate lot without a current, valid SC class assignment is non-conformant and its results MUST NOT be used to commission an SCR zone.

R-TRSQ-05 The SC class of the qualification lot MUST be recorded in the Qualification Record (§14.2). If the SC class changes during the qualification procedure (due to re-classification), the gate currently in progress MUST be re-executed under the new class's acceptance criteria.

4. Prerequisites and Entry Conditions#

4.1 Pre-Qualification Checklist#

R-TRSQ-06 Before the L1 gate is opened, all of the following entry conditions MUST be satisfied and documented in the Qualification Record:

R-TRSQ-07 Entry condition EC-01 requires that the SC class be SC-II or better. A lot classified SC-III MUST NOT enter TRS qualification — it is ineligible for temporal manufacturing and no qualification data produced from it has normative standing.

4.2 Reference Patterns#

R-TRSQ-08 All four qualification gates use a common set of reference address patterns drawn from the FSCP (Full-Spectrum Contrast Pattern) defined in docs/post-ASML_era/TCT_Protocol.md, §5.2, augmented with layer-specific test vectors defined in §7 through §10 of this procedure. The reference pattern set MUST be version- controlled and checksummed; the checksum MUST match the master pattern record in the fab's qualification management system before any gate begins.

4.3 Environmental Conditions#

R-TRSQ-09 All qualification gates MUST be executed with the CEC maintaining the following conditions throughout the gate:

R-TRSQ-10 If any CEC parameter exceeds its specification during a gate, the gate MUST be paused. The gate is resumed only after the CEC parameter returns within specification and is stable for ≥ 5 minutes. Pause events MUST be logged in the Qualification Record with timestamps.

5. Instrument Requirements#

5.1 Instrument Classes#

The following instrument classes are required for TRS qualification. Specific instrument instances MUST be identified by asset ID in the Qualification Record.

R-TRSQ-11 All instruments used in TRS qualification MUST have current calibration traceable to the calibration chain defined in their respective governing protocols (TAIS/ARS: docs/post-ASML_era/TCT_Protocol.md, §11; TRM/ISP/CGS: docs/post-ASML_era/The_TGI_Metrology_Standard.md, §12). Instruments with lapsed calibration MUST NOT be used; the gate is blocked until calibration is renewed.

R-TRSQ-12 The CJA (Commit Jitter Analyzer) and SSM (SLF Stability Monitor) are introduced in this procedure and are not separately defined in upstream metrology documents. Their minimum specifications are as stated in the table above. Fabs MUST characterize and document the calibration method for these instruments in their equipment qualification records before executing L4 gate measurements.

5.2 Instrument Cross-Registration#

R-TRSQ-13 All instruments used in a qualification gate MUST be co-registered to the same die coordinate reference before gate measurements begin, per docs/post-ASML_era/The_TGI_Metrology_Standard.md, §9.1 (R-INSTR-01 and R-INSTR-02). Cross-instrument coordinate registration error MUST be ≤ 2 nm (3σ) and MUST be verified by measurement of a qualified reference coupon at the start of each gate.

6. Test Coupon Requirements#

6.1 Coupon Specification#

R-TRSQ-14 TRS qualification coupons MUST satisfy all requirements of docs/post-ASML_era/TCT_Protocol.md, §4, with the following additional constraints:

• SC class minimum: SC-II or better (established by prior SC class assignment per §4.1 EC-01). SC-I coupons are preferred where availability permits.
• Coupon count: A minimum of one coupon per gate; four coupons per full qualification run. Additional coupons SHOULD be prepared as spares in the event of coupon failure during a gate.
• Coupon traceability: Each coupon MUST be identified by a coupon ID that is traceable to the lot and wafer from which it was diced, and that lot MUST have a valid SC class assignment.

R-TRSQ-15 Coupons used in gate L1 MUST NOT be reused in gates L2, L3, or L4. Each gate uses a fresh coupon. This requirement preserves measurement independence across gates: residual committed state from one gate must not confound measurements in a subsequent gate.

6.2 Coupon Preparation Sequence#

Before each gate, the gate's designated coupon MUST be prepared in the following order:

1. Surface inspection per docs/post-ASML_era/TCT_Protocol.md, §4.3 (R-COUP-05, R-COUP-06).
2. Prior injection check: ARS scan at five random sites confirms no structured address state.
3. Load into CEC; thermal stabilization ≥ 20 minutes at 25.0 °C ± 0.1 °C.
4. TAIS calibration check per §5 of this procedure.
5. ARS calibration check per §5 of this procedure.
6. Log coupon ID, preparation timestamp, and CEC initial conditions in the Qualification Record.

R-TRSQ-16 A coupon that fails the prior injection check (step 2) MUST be discarded and replaced. A coupon showing structured address state from prior use is non-conformant for TRS qualification regardless of its SC class.

7. L1 Intent Layer Qualification#

7.1 Purpose#

The L1 Intent Layer is responsible for converting logical design intent — expressed as a directed acyclic graph (DAG) of temporal operations with causal dependencies — into coherence-referenced temporal signals delivered to L2. The L1 qualification gate verifies that this conversion is performed with sufficient fidelity: that the temporal signals output by L1 accurately represent the intent map and carry the correct address assignments, dependency declarations, and scheduling constraints.

7.2 L1 Reference Test Vectors#

The L1 gate uses a set of eight Intent Test Vectors (ITVs), each a fully specified intent map with known correct L1 output. ITVs are defined in the qualification management system and MUST be version-locked to the current qualification procedure revision.

R-TRSQ-17 All eight ITVs MUST be executed in the L1 gate. Partial execution of the ITV set is non-conformant. If any ITV fails, the full ITV set MUST be re-executed after remediation, not only the failing ITV.

7.3 L1 Measurement Protocol#

For each ITV:

1. Load the ITV intent map into the L1 system under test.
2. Command L1 to generate the corresponding coherence-referenced output signals.
3. Capture the output signals using the TAIS operating in signal-capture mode.
4. Compare captured output signals against the ITV reference output using the Intent Signal Comparator (ISC) function of the TAIS.
5. Compute the Intent Signal Fidelity (ISF) metric for this ITV (§7.4).
6. Record ITV result, ISF value, and any signal anomalies in the Qualification Record.

R-TRSQ-18 The maximum elapsed time from ITV load to captured signal readback MUST be ≤ 2 coherence cycles. Intent signals that require more than 2 cycles to produce indicate an L1 processing bottleneck that must be remediated before qualification can proceed.

7.4 Intent Signal Fidelity (ISF) Metric#

ISF quantifies the accuracy of the L1 output signal set relative to the ITV reference:

ISF = 1 − (1/N_ops) × Σ_i |τ_output,i − τ_reference,i|

Where:
  N_ops         = total operation count in the ITV intent map
  τ_output,i    = temporal address carried in the L1 output signal for operation i
  τ_reference,i = temporal address specified in the ITV reference output for operation i
  ISF           ∈ [0, 1]; 1.0 = perfect fidelity

R-TRSQ-19 ISF MUST be computed per ITV and for the aggregate across all eight ITVs. Both the per-ITV and aggregate ISF values MUST be recorded in the Qualification Record.

7.5 L1 Dependency Declaration Accuracy#

In addition to ISF, the L1 gate verifies that dependency declarations in the L1 output signal set correctly reflect the DAG edges in the input intent map.

R-TRSQ-20 For each ITV containing dependency edges (ITV-02 through ITV-08), the Qualification System MUST verify that:

• Every declared edge in the ITV intent map produces a corresponding dependency signal in the L1 output.
• No spurious dependency signals appear in the L1 output that are not present in the intent map.
• The direction of each dependency signal (predecessor → successor) is correct.

Dependency declaration accuracy MUST be reported as a fraction: (correctly declared edges) / (total edges in ITV intent map). A value of 1.0 is required for L1 gate passage.

7.6 Error Detection Verification (ITV-07)#

R-TRSQ-21 ITV-07 presents a cyclic graph to the L1 system. The L1 system MUST detect the cycle and refuse to generate output signals, instead returning a defined error code. An L1 system that processes ITV-07 and produces output signals without error detection has failed this requirement and the L1 gate, regardless of all other metrics.

7.7 L1 Gate Acceptance Summary#

8. L2 Sequencing Layer Qualification#

8.1 Purpose#

The L2 Sequencing Layer receives the coherence-referenced output from L1 and produces an ordered schedule of commit operations, respecting all causal dependencies and assigning each operation to a specific coherence slot. The L2 qualification gate verifies that this scheduling is performed correctly: that the produced schedule is causally valid, slot assignments are consistent with the coherence budget, and scheduling latency is within specified bounds.

8.2 L2 Reference Test Vectors#

The L2 gate uses eight Sequencing Test Vectors (STVs), each a fully specified L1 output signal set with a known correct L2 schedule.

R-TRSQ-22 All eight STVs MUST be executed. STV-06 verifies the deferred-slot procedure (SCR Specification §5.4); the SCAA MUST confirm that deferred operations are placed in the correct re-assigned slot without exceeding D_max.

8.3 L2 Measurement Protocol#

For each STV:

1. Inject the STV signal set into the L2 system under test via the L1 output interface.
2. Command L2 to produce a commit schedule.
3. Capture the produced schedule: operation-to-slot assignment table, causal ordering verification flags, and scheduling latency.
4. Compare against the STV reference schedule using the Schedule Comparator function.
5. Compute Sequencing Order Integrity (SOI) and scheduling latency for this STV.
6. Record all results in the Qualification Record.

R-TRSQ-23 Maximum scheduling latency — elapsed time from STV injection to commit schedule output — MUST be ≤ T_graph per the definition in docs/post-ASML_era/ The_TRS-Aware_PDK_Specification.md, §11.1. Schedules delivered after T_graph produce authorization timing violations at the L4 Commit Arbiter.

8.4 Sequencing Order Integrity (SOI) Metric#

SOI = 1 − (N_violations / N_dependencies)

Where:
  N_violations  = number of dependency edges in the STV where the successor
                  operation is assigned to a slot ≤ the predecessor's slot
  N_dependencies = total dependency edges in the STV
  SOI           ∈ [0, 1]; 1.0 = no violations

R-TRSQ-24 SOI MUST be 1.000 for every STV. An SOI value below 1.000 means that at least one causal ordering constraint was violated by the schedule; any such violation is a disqualifying failure.

8.5 Oversubscription and Deferral Detection#

R-TRSQ-25 STV-08 presents an oversubscribed slot to L2. L2 MUST detect the oversubscription and either re-assign the excess operation to the next available slot or return a rejection error. An L2 system that produces a schedule assigning N_slot_max + 1 operations to a single slot without detection has failed this requirement.

R-TRSQ-26 STV-06 requires that L2 correctly handle an operation whose predecessor remains unresolved for 3 cycles. L2 MUST defer the dependent operation for each cycle the predecessor is unresolved and schedule it in the first available slot after resolution. Deferral count MUST be accurately tracked and MUST match the expected value in the STV reference.

8.6 L2 Gate Acceptance Summary#

9. L3 Resolution Layer Qualification#

9.1 Purpose#

The L3 Resolution Layer applies the apodization envelope to each scheduled commit operation and resolves the commit signal to the spatial coordinates of the target substrate site. The L3 qualification gate verifies that apodization is applied correctly, that address spacing enforcement is active, and that the resolved signals are spatially uniform across the substrate extent.

9.2 L3 Reference Test Vectors#

R-TRSQ-27 All eight RTVs MUST be executed. RTV-08 uses the FSCP reference pattern from the TCT Protocol to establish end-to-end resolution fidelity — the L3 output for RTV-08 MUST produce AER values consistent with the qualification substrate's SC class at each FSCP spacing level.

9.3 L3 Measurement Protocol#

For RTV-01 through RTV-07:

1. Inject the RTV schedule into L3 via the L2 output interface.
2. Command L3 to apply apodization and resolve commit signals.
3. Capture the resolved commit signal parameters: apodization envelope shape, side-lobe levels, spatial coordinates of resolved site, and address assignment.
4. For rejection RTVs (RTV-03), verify that L3 returns a rejection code and does not produce a resolved commit signal.
5. Record all parameters and pass/fail determinations in the Qualification Record.

For RTV-08:

1. Inject the FSCP reference pattern schedule into L3.
2. Command L3 to resolve all 49 commit signals.
3. Commit all resolved signals to the gate's test coupon using the TAIS in L3-driven mode.
4. Read back all committed addresses using the ARS.
5. Compute AER at each FSCP spacing level.
6. Compare AER values against the substrate SC class acceptance thresholds in §12.

R-TRSQ-28 The apodization envelope measured in RTV-01 and RTV-05 MUST match the W_apod and n_apod parameters from the TSPS (TRS Stack Parameter Set) for the qualification substrate's SC class, within ±5% on W_apod and ±10% on n_apod. Deviations beyond these tolerances indicate L3 misconfiguration.

9.4 Resolution Uniformity (RU) Metric#

Resolution uniformity measures the consistency of the apodization envelope across the die extent, using data from RTV-06 (center vs. corner sites):

RU = 1 − |ISF_center − ISF_corner| / ISF_min

Where:
  ISF_center = intent signal fidelity at the die center site
  ISF_corner = intent signal fidelity at the die corner site
  ISF_min    = minimum ISF threshold for the SC class (§12)
  RU         ∈ (−∞, 1]; values below 0 indicate corner ISF below ISF_min

R-TRSQ-29 RU MUST be ≥ 0.90 for SC-I qualification and ≥ 0.80 for SC-II qualification. An RU value below these thresholds indicates that spatial non-uniformity in the L3 resolution layer would produce position-dependent fidelity variations exceeding the acceptable margin.

9.5 Side-Lobe Level Verification#

R-TRSQ-30 The maximum side-lobe level of the apodized commit signal, measured in RTV-05, MUST be ≤ SLL_max from the TSPS for the qualification substrate's SC class. A side-lobe level exceeding SLL_max risks committing spurious partial addresses at the neighboring substrate sites, producing systematic TAOE.

9.6 TGI Proximity Rule Enforcement#

R-TRSQ-31 RTV-07 presents a commit site within 5 nm of z_c. L3 MUST apply the SC_eff-derived Δτ_eff for that site rather than the SC_bulk-derived Δτ_eff, per TPR-001 in the PDK Specification. The Qualification System MUST verify that the address spacing used for RTV-07 resolution is consistent with SC_eff, not SC_bulk.

9.7 L3 Gate Acceptance Summary#

10. L4 Commit Layer Qualification#

10.1 Purpose#

The L4 Commit Layer executes the physical commitment of temporal addresses to the substrate. It contains the Temporal Commit Units (TCUs), the Commit Arbiter (CA), and the SCR clock interface. The L4 qualification gate verifies that commit operations are executed with the correct timing relative to the SCR coherence clock, that the Synchronization Lock Frame (SLF) is acquired and held stably, and that post-commit address readback confirms the committed state is within the substrate's SC class fidelity limits.

10.2 L4 Reference Test Vectors#

R-TRSQ-32 All eight CTVs MUST be executed. CTV-06 and CTV-07 together establish SLF acquisition and stability; both MUST pass before the L4 gate is considered complete.

10.3 L4 Measurement Protocol#

Commit jitter measurement (CTV-01, CTV-02, CTV-03):

1. Inject the CTV schedule into L4 via the L3 output interface.
2. Trigger commit operations per the schedule.
3. Measure the commit timing of each operation using the CJA (Commit Jitter Analyzer), referenced to the SCR coherence clock.
4. Compute commit jitter CJ for each slot:

CJ = σ(t_commit − t_slot_boundary)

Where:
  t_commit         = measured commit timestamp (ns)
  t_slot_boundary  = expected slot boundary time from the SCR clock (ns)
  σ(·)             = standard deviation over N_commits at this slot
  CJ               ∈ [0, ∞) ns

5. Record CJ per slot and aggregate CJ across all CTVs in the Qualification Record.

Post-commit readback (CTV-01 through CTV-05):

After each CTV commit sequence:

1. Allow the T_auth setup window to elapse after the final commit.
2. Read back all committed addresses using the ARS.
3. Compute the post-commit AER:

AER_commit = N_error_addresses / N_total_addresses

4. Record AER_commit and compare against the SC class threshold in §12.

SLF tests (CTV-06, CTV-07, CTV-08):

CTV-06: From a cold (unacquired) SLF state, command the L4 system to acquire SLF lock. Measure time-to-lock using the SSM. Record against the acceptance limit in §10.4.

CTV-07: With SLF locked, issue 1000 consecutive coherence cycles of nominal commit load (50% slot occupancy). Monitor SLF stability with the SSM throughout. Record any lock-loss events.

CTV-08: With SLF locked, remove the CCG primary reference to trigger holdover. Monitor the frequency accuracy of the holdover oscillator using the SSM for 100 ms. Verify CCG re-locks to the primary reference upon restoration within one SLF acquisition cycle.

10.4 Commit Arbiter Dependency Enforcement#

R-TRSQ-33 CTV-04 presents a commit operation whose predecessor has not yet been acknowledged. The CA MUST withhold authorization for the dependent operation until the predecessor acknowledgment is received. The Qualification System MUST verify that the dependent operation is not committed early and that the authorization is issued within T_auth after predecessor acknowledgment.

R-TRSQ-34 If the CA issues authorization for the dependent operation before the predecessor acknowledgment is received, the L4 gate fails immediately. This failure mode indicates a CA arbitration defect that would produce causal order violations in production.

10.5 SLF Acceptance Criteria#

R-TRSQ-35 Any SLF lock-loss event during CTV-07 for an SC-I qualification is an immediate L4 gate failure. For SC-II qualification, one lock-loss event is tolerated only if recovery completes within 2 coherence cycles and no commit operation was in the commit window at the moment of loss.

10.6 L4 Gate Acceptance Summary#

11. Full-Stack Integration Test#

11.1 Purpose#

The Full-Stack Integration Test verifies that all four TRS layers function correctly as a composed system. It exercises end-to-end flows that cross all layer boundaries in a single continuous test sequence, detecting failure modes that arise from inter-layer interaction rather than individual layer defects.

11.2 Integration Test Procedure#

R-TRSQ-36 The Full-Stack Integration Test MUST use the following sequence:

1. Load the Full-Stack Reference Intent Map (FSRIM) into L1. The FSRIM is a qualification-management-controlled intent map of 512 operations with a mix of sequential chains, parallel clusters, cross-zone dependencies, and boundary-address operations. Its checksum MUST be verified before loading.

2. Command the full TRS stack (L1 → L2 → L3 → L4) to process the FSRIM from intent to committed addresses on the integration test coupon, without any intermediate operator intervention.

3. Capture all inter-layer signals at the L1/L2, L2/L3, and L3/L4 interfaces throughout the processing sequence. These captures are used to detect inter-layer communication defects.

4. Read back all 512 committed addresses using the ARS after the full sequence completes.

5. Compute the Full-Stack AER (AER_fs) from the readback results.

6. Compute the End-to-End Latency (EE_latency) — total wall-clock time from FSRIM injection to last committed address acknowledged — and compare against the expected value derived from the TSPS sequencing parameters.

R-TRSQ-37 The Full-Stack Integration Test MUST be run three times on three separate integration test coupons. The AER_fs and EE_latency results across all three runs MUST each be within the acceptance limits of §11.3. A single run outside the limit constitutes a full-stack failure.

11.3 Full-Stack Acceptance Criteria#

Where N_folds is the expected number of fold cycles required to process the FSRIM at the qualification substrate's SC class and N_slot_max.

R-TRSQ-38 Inter-layer signal anomalies are defined as any deviation from the expected signal timing, ordering, or content at any inter-layer interface capture point. A detected anomaly is a Full-Stack Integration failure regardless of whether the committed AER passes.

12. Acceptance Criteria by SC Class#

12.1 Consolidated Acceptance Criteria Table — SC-I#

The following acceptance criteria apply when the qualification substrate's SC class is SC-I (SC > 0.92).

12.2 Consolidated Acceptance Criteria Table — SC-II#

The following acceptance criteria apply when the qualification substrate's SC class is SC-II (0.75 ≤ SC ≤ 0.92).

12.3 Dependency Declaration and Error Detection — Class-Independent#

R-TRSQ-39 The following criteria apply regardless of SC class and carry no relaxation between SC-I and SC-II:

• L1 dependency declaration accuracy: 1.000
• L1 ITV-07 error detection: PASS
• L2 SOI: 1.000
• L2 STV-08 oversubscription detection: PASS
• L4 CTV-04 CA dependency enforcement: PASS
• Full-stack inter-layer anomaly count: 0

These are structural correctness requirements. They are not material-property-dependent and cannot be relaxed by any combination of SC class, fab waiver, or exceptional circumstance.

13. Disqualification, Remediation, and Re-Qualification#

13.1 Gate Failure Disposition#

When any gate metric fails to meet its acceptance criterion:

R-TRSQ-40 The gate is marked FAILED. The Qualification Record MUST record:

• The gate identifier (L1/L2/L3/L4/Full-Stack)
• The specific metric(s) that failed
• The measured value(s)
• The acceptance criterion that was not met
• The timestamp of the failure

R-TRSQ-41 No subsequent gate may proceed. The qualification sequence halts. All substrates associated with this qualification run MUST be placed on hold pending remediation.

R-TRSQ-42 The failure MUST be escalated to the TRS Qualification Engineer within 4 hours. The escalation MUST include the Qualification Record excerpt for the failing gate.

13.2 Remediation Categories#

Failures are categorized into three remediation tracks:

R-TRSQ-43 Track determination MUST be made by the TRS Qualification Engineer within 24 hours of escalation receipt. Track A and B remediations proceed under an approved remediation plan. Track C termination requires SCAA sign-off and is recorded as a qualification termination, not a qualification failure.

13.3 Periodic Re-Qualification#

R-TRSQ-44 Periodic re-qualification is required at the following intervals:

R-TRSQ-45 Periodic re-qualification uses the same procedure as initial qualification. There is no abbreviated re-qualification path.

14. Documentation and Sign-Off#

14.1 Qualification Record Structure#

R-TRSQ-46 A Qualification Record MUST be maintained throughout the entire procedure and MUST contain, in addition to gate-specific data recorded per §7 through §11:

14.2 Sign-Off Authority Chain#

R-TRSQ-47 The Qualification Record MUST be signed by the following authorities before it is submitted to the SCR commissioning workflow:

R-TRSQ-48 All signatures MUST be cryptographic (GPG or equivalent PKI-based), tied to the signer's authenticated identity in the fab's identity management system. Plain-text name entries are not valid for production qualification records.

14.3 Qualification Certificate#

R-TRSQ-49 Upon successful completion of the procedure and all sign-offs, the TRS Qualification Authority issues a TRS Qualification Certificate that MUST include:

• Qualification Record session ID
• Substrate lot ID and SC class
• SCR zone ID for which qualification is valid
• Date of qualification
• Expiry date (12 months from date of qualification per §13.3)
• TSPS parameter set version qualified against
• TRS Qualification Authority identifier and signature

R-TRSQ-50 The certificate MUST be registered in the fab's qualification management system and MUST be accessible to the SCR zone commissioning workflow before any wafer lot enters production on the qualified zone.

14.4 Retention#

R-TRSQ-51 Qualification Records and Qualification Certificates MUST be retained for a minimum of five (5) years from the date of issuance, or for the lifetime of the process node, whichever is longer. Records from failed qualifications MUST be retained under the same policy and MUST NOT be deleted or anonymized.

15. Integration with SCR Commissioning#

15.1 Qualification as the SCR Commissioning Gate#

The TRS Qualification Certificate is the primary enabling document for SCR zone commissioning. No SCR zone may proceed to commissioning under docs/fab/SCR_Zone_Config.md without a valid, current certificate for the substrate lot and zone combination.

R-TRSQ-52 The SCR commissioning workflow MUST verify that a valid Qualification Certificate exists for the target zone before opening any CCG, CDN, or CA configuration interface. Access to commissioning configuration without a valid certificate is a process violation.

15.2 Parameter Handoff to SCR Commissioning#

The following parameters from the TRS Qualification Record are consumed directly by the SCR commissioning workflow:

R-TRSQ-53 The SCR commissioning team MUST extract these parameters from the Qualification Record directly and MUST NOT use generic or design-time estimates in their place. Parameters derived from measurement are more accurate and provide better timing margin prediction than pre-qualification estimates.

15.3 PDK Generation Dependency#

R-TRSQ-54 The TRS-Aware PDK generation workflow requires a completed Qualification Record session ID as an input (PDK Specification §11.2, R-GEN-01). The PDK generation tool MUST reject any generation request that does not reference a current, signed Qualification Record. PDKs generated without a valid qualification reference are provisional and MUST carry the PROVISIONAL flag.

15.4 Re-Qualification Impact on Active PDK Releases#

When a re-qualification event occurs (§13.3):

R-TRSQ-55 If the re-qualification produces TSPS parameter values that differ from those used to generate the current active PDK by more than the minor-revision threshold (PDK Specification §14.2), a new PDK minor version MUST be generated using the updated qualification data before new design starts are accepted on the re-qualified zone.

R-TRSQ-56 Designs signed off under the prior PDK version continue to be valid for tape-out on the re-qualified zone, provided the re-qualification TSPS changes do not cause any timing paths to violate their margins when re-evaluated with the updated parameters. If any path's slack changes by more than 10% due to re-qualification parameter updates, the affected design MUST be re-checked.

16. Glossary#

17. Related Documents#

This document is part of the TriadicFrameworks canonical reference set. Proposed revisions must be submitted via pull request to the docs/fab/ directory with a linked issue describing the change rationale. Revisions to §12 (Acceptance Criteria by SC Class) require simultaneous updates to docs/materials/SC_Classification.md (§4) and docs/post-ASML_era/The_TRS-Aware_PDK_Specification.md (§13.2) and a cross-impact analysis confirming that no qualification that was previously passing would fail under the revised criteria, or that any such retroactive impact is explicitly addressed in the revision.